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Si 5 0 2 3 - EVB
E VALUATION B OARD FOR Si5023 SiPHY? M ULTI -R ATE
S O N E T / S D H C L O C K A N D D A TA R E C O V E R Y I C
Description
Features
The Si5023 evaluation board provides a platform for
testing and characterizing Silicon Laboratories’ Si5023
SiPHY? multi-rate SONET/SDH clock and data
recovery IC. The Si5023 CDR supports OC-48/12/3,
STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC rates.
All high-speed I/Os are ac coupled to ease interfacing to
industry standard test equipment.
Functional Block Diagram
VDD
210 ?
!
!
!
Single 3.3 V power supply
Differential I/Os ac coupled
Simple jumper configuration
Jitter
Analyzer
Pulse
Generator
Pattern
Generator
348 ?
Z C = 50 ?
Z C = 50 ?
Z C = 50 ?
Z C = 50 ?
+
REFCLK
–
+
DATAIN
–
+
CLKOUT
–
Si5023
+
DATAOUT
–
Z C = 50 ?
Z C = 50 ?
Z C = 50 ?
Z C = 50 ?
Scope
Pattern
Z C = 50 ?
RATESEL0
+ RATESEL1
LTR
REFCLK
LOS
+
LOL
CLKOUT
Z C = 50 ?
Analyzer
CLKDSBL
Z C = 50 ?
–
DSQLCH BER_ALM –
RESET/CAL
Si5023
Z C = 50 ?
Test Points
BER_MON
Z C = 50
Jumpers ?
Z C = 50 ?
+
DATAIN
–
+
DATAOUT
–
Z C = 50 ?
Z C = 50 ?
5k
LOS_LVL
REXT
RATESEL0
RATESEL1
LTR
SLICE_LVL
DSQLCH
RESET/CAL
BER_LVL
CLKDSBL
LOS
LOL
BER_ALM
10 k ?
Test Points
Si5023-EVB Rev B
Rev. 1.1 1/04
Copyright ? 2004 by Silicon Laboratories
Si5023-EVB-11
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